Microprocessor clock frequency (FCLK) is typically based on expected worst-case operating parameters such as supply voltage (VCC) droop and temperature. However, since operating parameters are normally not actually at the worst-case extremes, the operating FCLK may be unnecessarily limited. This is illustrated in FIGS. 1A and 1B.
FIG. 1A shows a conventional path where data is driven through a master-slave flip-flop (MSFF) 102 and logic components 104 to a receiving master-slave flip-flop 106. FIG. 1B is a timing diagram illustrating arrival times of the input data (D) to the receiving flip-flop 106 during worst-case dynamic variations and nominal conditions. Within the presence of worst-case dynamic variations, the input data to the receiving flip-flop must arrive a setup time prior to the rising clock edge to ensure correct functionality. In comparison, the input data for the same path arrives much earlier during nominal conditions. The difference between the input data arrival times for these two cases represents an effective timing guardband for dynamic variations.
FIG. 1C shows a conventional circuit to replace flip-flops 106, e.g., in critical path circuits, to account for dynamic extremes and allow for FCLK to be raised. This circuit mitigates the impact of infrequent dynamic variations and transistor aging on FCLK by employing error-detection circuitry to detect late transitions at the input of the sequential (MSFF in this case). The error detection circuitry includes a latch 112 and an XOR gate 116. In the depicted case, the MSFF is a rising edge triggered flip-flop, so latch 112 is transparent when the clock is High. In operation, the XOR gate 116 compares the flip-flop and latch outputs to produce an error signal (ERROR) if they are different, which occurs when late arriving data fails to get clocked through the flip-flop 114 but is passed through the latch to the XOR gate. The error signal is then propagated to the micro-architecture level to enable error recovery.
Unfortunately, this approach is costly in terms of consumed clock energy since an additional latch in conjunction with the MSFF is employed. In addition, the flip-flop is susceptible to datapath metastability issues, whereby a timing error may be undetected. Since undetected errors can normally not be tolerated, a metastability detector is required, resulting in substantial design overhead in both area and power.
Accordingly, a new approach is desired.